The present disclosure relates generally to the field of semiconductor manufacturing. More particularly, the present disclosure relates to methods for plating metal gate conductors on semiconductor devices and semiconductors formed thereby.
The continuing push for high performance and high density in the ultra large scale integrated circuits (ULSI) industry demands new device technologies to scale device dimension and new methods for manufacturing the new devices.
For example, the demand for increased device performance is particularly strong in the design and fabrication of field effect transistors (FET's). However, scaling FET's to attain higher device performance and density can increase the cost and difficulty of many manufacturing steps.
One type of FET that has been proven to provide increased device performance is a fin Field Effect Transistor (“finFET”). In a finFET, the body of the transistor is formed from a vertical structure, generally referred to as a “fin”. The gate conductors of the finFET are then formed on one or more sides of the fin. Unfortunately, the formation of gate conductors on the vertical fin has proven increasingly difficult as the density of the finFET technology is increased. For example, the formation of gate conductors on the vertical fin requires specially-optimized lithography and etching to define the gate, which have proven difficult and/or expensive in many manufacturing processes.
Accordingly, it has been determined by the present disclosure that there is a need for methods of producing new semiconductor device features that overcome, mitigate, and/or avoid one or more of the aforementioned drawbacks and deficiencies of the prior art.